Novel Approaches to the Timing of FFC-NMR experiments

 A.Galkin, D.Canina, S.Sykora, G.M.Ferrante
Stelar Srl, Via E. Fermi 4, 27035 Mede (PV), Italy.

presented at

4th Conference on Field Cycling NMR Relaxometry, Torino (Italy), May 26-28, 2005.

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Compared with a HR-NMR spectrometer, a Fast-Field-Cycling NMR Relaxometer imposes a number of extra requirements on the timing of acquisition sequences [1]. This is because the field-switching cycles become more sophisticated (field waveforms profiling) and because FFC-NMR is used to investigate all kinds of samples, including liquids, solids, granular materials and combinations of them with very different FIDs (required sampling rates range from 1kHz to 10 MHz).

Consider, for example, samples with several phases (e.g., a rigid matrix, a bulk water phase, and an adsorbed water layer). In such cases it would be convenient to split the FID into two or more temporal windows and apply in each of them quite different signal-acquisition parameters (such as the dwell time and filter width values). In this way one could, in fact, optimize the final S/N ratio of each sample component. This approach implies, however, a real-time control of the dwell time, the filter settings and other receiver parameters.

With the ongoing development of variable-field relaxometry, we expect that there will soon arise the need for a second and even third RF irradiation channel and that all such channels will need to be synchronized with the rest of the system. We provide dynamically controlled (not just digitally pre-settable) frequency, phase and amplitude of all the channels and offer the User additional possibilities such as composite, profiled, and chirp pulses.

To meet all these requirements, we have adopted a number of very innovative engineering solutions, centered around the modern FPGA based system-on-chip (SOC) concept and trying to place all the most speed critical discrete electronic devices close to each other on the same board. The heart of the system is a powerful FPGA chip running at up to 210 MHz clock speed. A single chip system provides us with considerable timing advantages such as direct signal digitization up to 90 MHz and a complete real time control of all relevant acquisition parameters with temporal resolution of 20 ns. The FPGA chip is located on a PCI board together with pulser controlled ADC, DAC's, RF attenuators, RAM and relative analog and digital circuits.

In order to control slower devices such as magnetic field pulse shapers it was found more expedient to use dedicated small pulse sequencers placed on the corresponding slow device's boards and remotely synchronized from the main pulser.

The FPGA system chip incorporates:

  • Quadrature Digital Down Converter (phase detector), as well as pulser controlled digital filter blocks.
  • A versatile pulser controlled data accumulator with an ample choice of accumulation modes.
  • Versatile, pulser-controlled data accumulator with an ample choice of accumulation modes.
  • Three independent, pulser-controlled digital RF-generation channels.
  • Safety interlocks and external events controller interfaced with pulser.
  • Pulse sequences generator, implemented as a hard-wired sequence-timing sub-processor with 128 bits wide "words", specifically designed to handle all the tasks discussed above as well as many others. The generator has 96 output channels available for hardware control which permit synchronization with other boards and external devices. It supports run-time re-programming, unconditional and conditional jumps and execution of sub-sequences. It also supports nested cycles to a depth of 7 levels, ensuring very compact and fast loading sequence programs. The running sequences can be dynamically updated and reprogrammed. The sequencer can react in sophisticated ways to real time internal and external events such as signal overflows, safety interlocks and timing triggers.


  • G.Ferrante, S.Sykora, Technical Aspects Of Fast Field Cycling,
    in Adv.Inorg.Chem., Eds. R.van Eldik,I.Bertini, 2005, 57, 405-470.
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